1. Field of the Invention
The present invention relates to a socket used for an evaluation device and an analyzing device of a semiconductor device.
2. Description of the Background Art
Conventionally, when failure analysis and performance evaluation are performed on a semiconductor device, the semiconductor device is actually operated by applying a test pattern from a signal generator to the semiconductor device, while an electron beam is also applied onto the top face of the semiconductor device so that an secondary electron image is observed by detecting secondary electrons generated from the top face by using a detector. Moreover, light emission/heat generating analysis and an analysis using a laser and the like have been performed through an approach from the top face of a semiconductor device. Here, the semiconductor device is molded in an IC chip, and a package into which the IC chip is sealed by resin is attached to a socket (hereinafter, referred to as “top face exposed-type socket” in this specification”) in such a manner that a top face of the package faces upward (that is, facing the detector side).
However, along with the developments of a wire layer structure having multiple layers and various types of semiconductor devices such as LOC (Lead On Chip), CSP (Chip Scale Package) and Flip Chip BGA, it becomes difficult to accurately perform the failure analysis or the like through an approach from the top face of IC chips. For this reason, in recent years, the failure analysis or the like is performed through an approach from the rear face of IC chips.
Here, a technique relating to failure analyses of semiconductor devices has been disclosed in, for example, the Japanese Patent Application Laid-Open No. 11-111759 (1999).
Conventionally, when failure analysis or the like is performed on a general-purpose package such as a QFP (Quad Flat Package), SOP (Small Outline Package) and DIP (Dual Inline Package) through an approach from the rear face of a chip, a method has been used in which the chip rear face is exposed by machining the rear face of the top face exposed-type socket to form an opening therein. However, the problem with this method is that it sometimes becomes difficult or impossible to perform the machining process to form an opening due to socket leads that cause hindrance. Moreover, even in the case when the chip rear face is exposed, since the distance from the rear face of the socket to the rear face of the chip is long, it is not possible to use a recently-developed high-performance detector having a working distance of not more than 1 mm.
Another method has been proposed in which lead wires are directly connected to the package leads by using solder or clips. However, in this method, it becomes impossible to connect lead wires to all the leads of a recently-developed package having a several hundreds pins with narrow pitches, resulting in a failure to actually operate the semiconductor device appropriately. Moreover, as the number of lead wires increases, the lead wires come to cover the IC chip, with the result that it is not possible to use a high-performance detector having a working distance of not more than 1 mm in the same manner as described above.